Data Sheet
PowerPC® 750CXe RISC Microprocessor
Preliminary
Table 5-1. Signal Listing for the 256 PBGA Package
Signal Name
Pin Count
Active
High
Low
Low
Low
Low
Low
Low
Low
Low
High
High
Low
Low
Low
High
High
Low
Low
High
I/O
I/O
Notes
A0–A31
AACK
ARTRY
BG
32
1
Input
I/O
1
1
Input
Output
Output
Input
Output
Input
I/O
BR
1
CI
1
CKSTP_IN
CKSTP_OUT
DBG
1
2
1
1
DH0-DH31
DL0-DL31
GBL
32
32
1
I/O
I/O
HRESET
INT
1
Input
Input
Input
Input
Input
Input
Input
1
1
L1_TSTCLK
1
1,2,3
DBWO/L2_TSTCLK
1
1
LSSD_MODE
1
MCP
1
PLL_CFG[0-3]
4
OPTIONAL: 64/32-Bit Data Bus mode select.
This function will be set when HRESET transitions
(low to high). QACK: low = 64-bit mode, high = 32-bit
mode.
2
QACK
1
Low
Input
QREQ
SRESET
SYSCLK
TA
1
1
1
1
1
1
1
1
1
1
1
Low
Low
—
Output
Input
Input
Input
I/O
Low
Low
High
High
High
Low
High
Low
TBST
TCK
Input
Input
Output
Input
Input
Input
TDI
TDO
TEA
TMS
TRST
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. The CKSTP_OUT signal in test mode allows viewing the PowerPC 750CXe internal clocks.
The QACK signal allows selection of 32-bit mode.(See the PowerPC 750CXe User’s Manual for more information.)
3. L2-TSTCLK in normal mode is DBWO, for details, see Section 6.7.4 on Page 34.
PowerPC 750CXe Dimension and Physical Signal Assignments
Page 22 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
IBM [ IBM ]
