Data Sheet
PowerPC® 750CXe RISC Microprocessor
Preliminary
Table 5-3. Signal Locations
Signal
A0
Ball Location
C15
Signal
DH0
Ball Location
E2
Signal
DL0
Ball Location
W15
Y16
V14
Y15
W14
Y14
V13
Y13
Y12
V12
W12
Y11
Y10
W9
Signal
Ball Location
AACK
N18
A1
B16
D15
B17
A18
C20
D19
F17
E19
F18
F19
E20
G18
F20
G19
G20
P20
P19
R20
P18
DH1
D2
C1
A3
B4
D6
B5
C6
B6
A5
C7
A6
B7
A7
C8
A8
A9
C9
B9
A10
DL1
ARTRY
BG
M3
P1
N1
H1
T2
J3
A2
DH2
DL2
A3
DH3
DL3
BR
A4
DH4
DL4
BVSEL
CI
A5
DH5
DL5
A6
DH6
DL6
CKSTP_IN
CKSTP_OUT
DBG
A7
DH7
DL7
P2
M1
R2
E1
J2
A8
DH8
DL8
A9
DH9
DL9
GBL
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
DH10
DH11
DH12
DH13
DH14
DH15
DH16
DH17
DH18
DH19
DL10
DL11
DL12
DL13
DL14
DL15
DL16
DL17
DL18
DL19
HRESET
INT
L1_TSTCLK
F4
E3
F2
F3
F1
G2
G1
H2
1
DBWO/L2_TSTCLK
LSSD_MODE
MCP
V9
Y9
Y8
PLL_CFG0
PLL_CFG1
PLL_CFG2
PLL_CFG3
V8
Y7
W7
QACK (Also used for 64/32-bit DB
select.)
A20
T20
DH20
A11
DL20
Y6
K2
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
R19
R18
T19
R17
U19
V20
Y18
W17
U15
W16
V15
DH21
DH22
DH23
DH24
DH25
DH26
DH27
DH28
DH29
DH30
DH31
B12
C12
A12
A13
C13
A14
B14
A15
C14
A16
B15
DL21
DL22
DL23
DL24
DL25
DL26
DL27
DL28
DL29
DL30
DL31
V7
Y5
W6
V6
W5
U6
W4
Y3
V1
U2
T1
QREQ
SRESET
SYSCLK
TA
L1
K1
G3
M20
N20
T3
TBST
TCK
TDI
P3
TDO
TEA
N3
M2
TMS
TRST
TS
R3
R4
J19
L20
M19
M18
H18
H20
J20
J18
K20
R1
TSIZ0
TSIZ1
TSIZ2
TT0
TT1
TT2
TT3
TT4
WT
1. See Section 6.7.4 on Page 34 for a detailed discussion
PowerPC 750CXe Dimension and Physical Signal Assignments
Page 24 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
IBM [ IBM ]
