Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
4.3 Spread Spectrum Clock Generator (SSCG)
When designing with an SSCG, there are a number of issues that must be taken into account.
An SSCG creates a controlled amount of long-term jitter. In order for a receiving PLL in the 750CXe to
function correctly in this environment, it must be able to accurately track the SSCG clock jitter.
The accuracy with which the 750CXe PLL can track the SSCG is referred to as tracking skew. When
performing system timing analysis, the tracking skew must be added to or subtracted from the I/O timing
specifications, because the skew appears as a static phase error between the internal PLL and the SSCG
clock.
To minimize the impact on I/O timing, the following SSCG configuration is recommended:
• Down-spread mode ≤ 1% of the maximum frequency
• Modulation frequency of 30 kHz
• Linear sweep modulation or a modulation profile (Hershey Kiss™) as shown in Figure 4-2.
In this configuration, the tracking skew is less than 100ps.
Figure 4-2. Linear Sweep Modulation Profile
0%
Down spread
frequency
-1%
0µs
33.3µs
Time
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
Electrical and Thermal Characteristics
Page 11 of 36
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