Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
2. Overview
The PowerPC 750CXe is targeted for high performance, low power systems and a 60x bus. The PowerPC
750CXe also includes an internal 256KB L2 cache with on-board Error Correction Circuitry (ECC).
2.1 PowerPC 750CXe Block Diagram
Figure 2-1 shows a block diagram of the PowerPC 750CXe.
Figure 2-1. PowerPC 750CXe Block Diagram
Control Unit
Instruction Fetch
Branch Unit
Completion
32KB I-Cache
BHT /
BTIC
System
Dispatch
Unit
GPRs
FPRs
LSU
FPU
FXU1
FXU2
Rename
Buffers
Rename
Buffers
256KB
L2 Cache
60x
BIU
32KB D-Cache
L2 Tags
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
Overview
Page 5 of 36
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