Data Sheet
Preliminary
PowerPC® 750CXe RISC Microprocessor
1.2 Special Design Level Considerations/Features
The PowerPC 750CXe supports several unique features including those listed below. Section 6.7
“Operational and Design Considerations,” on page 33 provides a more detailed explanation of these features.
• Provides a 64- or 32-bit Data Bus mode (per setup of QACK pin).
• Supports 1.8V and 2.5V I/O signals.
• Uses a reduced pin list from earlier PowerPC 750 designs (see Table 5-2 on page 23).
• Data Bus Write Only (DBWO) shares a common pin with L2_TESTCLK.
• CHKSTP_OUT shares a common pin with CLK_OUT.
1.3 Ordering Information
For available devices, contact your local IBM sales office.
Figure 1-1 provides the IBM part numbering nomenclature for the PowerPC 750CXe.
Figure 1-1. IBM Part Number Key
IBM25PPC750CXEJP2012T
PowerPC 750 Family Member
Shipping Container
Reliability Grade
Enhanced Process
Design Revision Level
Package Type
Test Conditions
Performance Sort
Design Revision Level
Package Type
J = DD3.1
P = Plastic/Laminate Ball Grid Array
Q = Lead Free Plastic/Laminate Ball Grid Array
20 = 400MHz
Performance Sort
40 = 466MHz
50 = 500MHz
55 = 533MHz
70 = 600MHz
Test Conditions
Reliability Grade
Shipping Container
1 = +1.7V to +1.9V @ 105°C
2 = Special test conditions
2 = Grade 2, < 25FIT
3 = Grade 3, < 100FIT
T = Tray
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
General Information
Page 3 of 36
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