Data Sheet
Preliminary
PowerPC® 750CXr RISC Microprocessor
1.2 Special Design Level Considerations/Features
The PowerPC 750CXr supports several unique features including those listed below. Section 6.7
“Operational and Design Considerations,” on page 41 provides a more detailed explanation of these features.
• Provides a 64- or 32-bit Data Bus mode (per setup of QACK pin).
• Supports 1.8V and 2.5V I/O signals.
• Uses a reduced pin list from earlier PowerPC 750 designs (see Table 5-2 on page 31).
• Data Bus Write Only (DBWO) shares a common pin with L2_TESTCLK.
• CHKSTP_OUT shares a common pin with CLK_OUT.
1.3 Ordering Information
For available devices, contact your local IBM sales office.
Figure 1-1 provides the IBM part numbering nomenclature for the PowerPC 750CXr.
Figure 1-1. IBM Part Number Key
IBM25PPC750CXRKQ0124T
PowerPC 750 Family Member
Shipping Container
Reliability Grade
Enhanced Process
Design Revision Level
Package Type
Test Conditions
Performance Sort
Design Revision Level
Package Type
K = 4.0
Q = Lead Free Plastic/Laminate Ball Grid Array
01 = 300MHz, 333MHz w/o L2
03 = 300MHz, 333MHz
10 = 366 MHz
Performance Sort
20 = 400MHz
40 = 466 MHz
50 = 500MHz
55 = 533MHz
Test Conditions
2 = +1.8V to +1.9V @ 95°C for < 500MHz, +1.85V to +1.95V @ 95°C for 500 MHz and
533MHz
Reliability Grade
4 = Grade 4
T = Tray
Shipping Container
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
General Information
Page 11 of 43
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