Data Sheet
Preliminary
PowerPC® 750CXr RISC Microprocessor
2. Overview
The PowerPC 750CXr is targeted for high performance, low power systems and a 60x bus. The PowerPC
750CXr also includes an internal 256KB L2 cache with on-board Error Correction Circuitry (ECC).
2.1 PowerPC 750CXr Block Diagram
Figure 2-1 shows a block diagram of the PowerPC 750CXr.
Figure 2-1. PowerPC 750CXr Block Diagram
Control Unit
Instruction Fetch
Branch Unit
Completion
32KB I-Cache
BHT /
BTIC
System
Dispatch
Unit
GPRs
FPRs
LSU
FPU
FXU1
FXU2
Rename
Buffers
Rename
Buffers
256KB
L2 Cache
60x
BIU
32KB D-Cache
L2 Tags
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
Overview
Page 13 of 43
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