Data Sheet
PowerPC® 750CXr RISC Microprocessor
Figures
Figure 1-1. IBM Part Number Key ................................................................................................................ 11
Figure 2-1. PowerPC 750CXr Block Diagram .............................................................................................. 13
Figure 4-1. SYSCLK Input Timing Diagram .................................................................................................. 19
Figure 4-2. Linear Sweep Modulation Profile ............................................................................................... 20
Figure 4-3. Input Timing Diagram ................................................................................................................. 21
Figure 4-4. Mode Select Input Timing Diagram ............................................................................................ 22
Figure 4-5. Output Valid Timing Definition .................................................................................................... 23
Figure 4-6. Output Timing Diagram for PowerPC 750CXr ........................................................................... 24
Figure 4-7. JTAG Clock Input Timing Diagram ............................................................................................. 25
Figure 4-8. TRST Timing Diagram ............................................................................................................... 26
Figure 4-9. Boundary-Scan Timing Diagram ................................................................................................ 26
Figure 4-10. Test Access Port Timing Diagram ............................................................................................ 26
Figure 5-1. Pinout of the 256 PBGA Package as Viewed from Solder Ball side .......................................... 28
Figure 5-2. Side Profile View of PBGA ......................................................................................................... 29
Figure 5-3. Side Profile View Showing Exposed Cavity ............................................................................... 29
Figure 5-4. PowerPC 750CXr Microprocessor Ball Placement .................................................................... 30
Figure 6-1. PLL Power Supply Filter Circuit ................................................................................................. 36
Figure 6-2. Driver Impedance Measurement ................................................................................................ 37
Figure 6-3. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector ............................ 41
Figure 6-4. PBGA Package Thermal Model ................................................................................................. 42
sw_ds_750cxrLOF.fm
February 28, 2005
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