Table 5. Power Consumption
CPU Clock:
SYSCLK
Full-On Mode
Typical
Maximum
Nap Mode
Maximum
0.80
0.80
0.82
0.84
W
6.0
10.6
6.8
12.0
7.5
13.4
8.0
14.5
W
W
Processor Core Frequency
Unit
250 MHz
300 MHz
333 MHz
350 MHz
Notes:
1. These values apply for all valid PLL_CFG[0–3] settings and do not include output driver power (OVdd) or
analog supply power (AVdd). OVdd power is system dependent but is typically
≤
10% of Vdd. Worst-case
AVdd = 15 mW.
2. Typical power is an average value estimated at Vdd = AVdd = 1.9 V, OVdd = 3.3 V, T
j
= 25 °C in a system
executing typical applications and benchmark sequences. Typical power numbers should be used in
planning for proper thermal management.
3. Maximum power is estimated at Vdd = AVdd = 2.0 V, OVdd = 3.465 V,T
j
= 0 °C using a worst-case
instruction mix. These values should be used for power supply design.
4. Nap mode power consumption is estimated, and assumes no snoop activity.
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 604e. These specifications are for
250, 300, 333 and 350 MHz processor core frequencies. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. All
timings are specified respective to the rising edge of SYSCLK.
1.4.2.1 Clock AC Specifications
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105 °C
250 MHz
Num
Characteristic
Min
Processor frequency
VCO frequency
SYSCLK frequency
1
2, 3
4
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
measured at 0.9 V
200
400
28.6
10
1.0
40
Max
250
500
100
35
2.0
60
300 MHz
Min
250
500
35.7
10
1.0
40
Max
300
600
100
28
2.0
60
333 MHz
Min
283
566
40.4
10
1.0
40
Max
333
666
100
25
2.0
60
350 MHz
Unit
Min
300
600
42.8
10
1.0
40
Max
350
700
100
23
2.0
60
MHz
MHz
MHz
ns
ns
%
2
3
1
1
1, 6
Notes
8
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM
IBM [ IBM ]
