1.4.2.2 Input AC Specifications
Table 7 provides the input AC timing specifications for the 604e as defined in Figure 2. These
specifications are for 250, 300, 333 and 350MHz processor core frequencies.
Table 7. Input AC Timing Specifications1
Vdd = AVdd = 1.9=±100 mV dc, OVdd = 3.3 ±5% V dc, GND = 0 V dc, 0 ≤ T ≤ 105 °C
j
250, 300, 333, 350 MHz
Num
Characteristic
Unit Notes
Min
Max
7a
ARTRY, SHD, ABB, TS, XATS, AACK,BG, DRTRY, TA, DBG,
DBB, TEA, DBDIS, and DBWO valid to SYSCLK (input setup)
3.50
—
ns
7b
8
All other inputs valid to SYSCLK (input setup)7
SYSCLK to all inputs invalid (input hold)
2.50
–0.5
—
—
—
ns
ns
ns
2
9
Mode select input valid to HRESET (input setup for DRTRY)
8 * tsysclk
3, 4, 5,
6
10
HRESET to mode select input invalid (input hold for DRTRY)
–0.5
—
ns
3, 4, 5,
6
Notes:
1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 0.9 V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 2).
2. All other input signals include the following signals—all inputs except ARTRY, SHD, ABB, TS, XATS, AACK,
BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs.
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
4. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.
5. These values are guaranteed by design, and are not tested.
6. Note this is for configuration of the fast-L2 mode and the no-DRTRY mode.
7. Setup time is extended by 0.5 ns for these signals when Hysteresis On mode is enabled.
Figure 2 provides the input timing diagram for the 604e.
VM
SYSCLK
8
7
ALL INPUTS
VM = Midpoint Voltage (0.9 V)
Figure 2. Input Timing Diagram
10
PID9q-604e Hardware Datasheet
IBM
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM [ IBM ]
