Figure 3 provides the mode select input timing diagram for the 604e.
HRESET
VM
10
9
DRTRY
VM = Midpoint Voltage (0.9 V)
Figure 3. Mode Select Input Timing Diagram
1.4.2.3 Output AC Specifications
The output specifications of the 604e for both driving high and driving low depend on the
capacitive loading on each output and the drive capability enabled for that output. Additionally, the
timing specifications for outputs driving low also depend on the voltage swing required to drive to
0.4V. Table 8 provides the output AC timing specifications for a 5pF, 50 W transmission line load.
In order to derive the actual timing specifications for a given set of conditions, it is recommended
that IBIS simulation models be used. The IBIS models are currently based on device simulation
data. Compatibility mode specifications are provided to support PID9q-604e use in existing
designs. Contact the local IBM sales office for information on the availability of these models.
Table 8 provides the output AC timing specifications for the 604e (refer to Figure 4).
Table 8. Output AC Timing Specifications1
6
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3=± 5% V dc, GND = 0 V dc, 0 ≤ T ≤ 105 °C, drive mode [11]
j
250, 300, 333, 350 MHz
Num
Characteristic
Unit Notes
Compatibility
Mode
Min
Max
11
12
SYSCLK to output driven (output enable time)
0.75
—
—
0.75 Min
4.75 Max
ns
ns
2, 5
5
SYSCLK to TS, XATS, ARTRY, SHD, ABB and
DBB output valid
3.75
13
14
15
SYSCLK to all other signals output valid
SYSCLK to output invalid (output hold)
—
0.0
—
4.75
3.4
5.75 Max
0.5 Min
ns
ns
ns
5
2, 5
5
SYSCLK to output high impedance (all signals
except ARTRY, SHD, ABB, DBB, TS, and
XATS)
4.4 Max
16
17
SYSCLK to output high impedance TS, XATS
—
3.4
4.4 Max
ns
ns
5
4
—
1.0* tsysclk
1.0* tsysclk Max
SYSCLK to ABB and DBB high impedance
after precharge
18
SYSCLK to ARTRY and SHD high impedance
before precharge
—
3.4
4.4 Max
ns
5
9/17/99 Revision 1.4
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
11
IBM [ IBM ]
