1
2
3
4
4
CVih
VM
SYSCLK
CVil
VM = Midpoint Voltage (1.4 V)
Figure 2. SYSCLK Input Timing Diagram
3.1.2.2 60x Bus Input AC Specifications
Table 8 provides th e 60X bu s in pu t AC tim in g specification s for th e PPC740 an d
PPC750 as defin ed in Figu re 3 an d Figu re 4 . Input timing specifications for the L2 bus are
provided in Section 3.1.2.5, “L2 Bus Input AC Specifications“.
1
Table 8. 60X Bus Input Timing Specifications
Operating conditions are specified in Section Table 2., "Recommended Operating Conditions"
Num
Characteristic
Min
Max
Unit
Notes
10a
Address/Data/Transfer Attribute Inputs Valid to SYSCLK
(Input Setup)
2.5
—
ns
2
10b
10c
All Other Inputs Valid to SYSCLK (Input Setup)
3.0
8
—
—
ns
3
Mode Select Input Setup to HRESET (DRTRY,TLBISYNC)
tsysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute Inputs Invalid
(Input Hold)
1.0
—
ns
2
11b
11c
SYSCLK to All Other Inputs Invalid (Input Hold)
1.0
0
—
—
ns
ns
3
HRESET to mode select input hold (DRTRY, TLBISYNC)
4,6,7
Notes:
1. Input specifications are measured from the TTL level (0.8 to 2.0 V) of the signal in question to the 1.4V
of the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see
Figure 3 ).
2. Address/Data Transfer Attribute inputs are composed of the following--A[0-31], AP[0-3], TT[0-4],TBST,
TSIZ[0-2], GBL, DH[0-31), DL[0-31], DP[0-7].
3. All other signal inputs are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG,
DBWO, TA, DRTRY, TEA, DBDIS, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4 ).
5. tsysclk, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the
parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset
sequence.
10 of 44
PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
IBM [ IBM ]
