Table 7. Clock AC Timing Specifications (Continued)
Vdd = AVdd = 2.5
±
5% Vdc (= 3.3
±
5% Vdc for PID6). O Vdd = 3.3
±
5% Vdc. GND = 0 Vdc, 0
≤
Tj
≤
105°C.
PID6
Num
Characteristic
80 MHz
Min
4
SYSCLK duty
cycle
measured at
1.4 V
SYSCLK jitter
603e and
EM603e
internal PLL-
relock time
Notes:
40.0
Max
60.0
100 MHz
Min
40.0
Max
60.0
PID7v
166 MHz
Min
40.0
Max
60.0
PID7t
200 MHz
Min
40.0
Max
60.0
%
3
Unit
Notes
—
—
150
100
—
—
150
100
—
—
150
100
—
—
150
100
ps
µs
4
3,5
1.
Caution:
The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description
in Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term
combined) must be under
±150
ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during
the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time (100
µs)
during the power-on reset sequence.
1
4
4
CVih
VM
VM
VM
CVil
2
3
SYSCLK
VM = Midpoint Voltage (1.4 V)
Figure 1. SYSCLK Input Timing Diagram
603e and EM603e Hardware Specification
9
IBM [ IBM ]
