1.4.2.2 Input AC Specifications
Table 8 provides the input AC timing specifications for the 603e and EM603e as defined in Figure 1,
Figure 2, and Figure 3.
1
Table 8. Input AC Timing Specifications
Vdd = AVdd = 2.5 ± 5% Vdc (= 3.3 ± 5% Vdc for PID6). O Vdd = 3.3 ± 5% Vdc. GND = 0 Vdc, 0 ≤ Tj ≤ 105 °C.
PID6
80 MHz
PID7v
PID7t
100 MHz
166 MHz
200 MHz
Num
Characteristic
Unit
Notes
Min
Max Min Max Min Max Min Max
10a Address/data/transfer attribute
inputs valid to SYSCLK (input
setup)
3.0
—
2.5
—
2.5
—
2.5
—
ns
2
10b All other inputs valid to SYSCLK
(input setup)
5.0
—
—
4.5
—
—
4.0
8
—
—
4.0
8
—
—
ns
3
10c Mode select inputs valid to
HRESET (input setup) (for
8*tsysclk
tsysclk 4, 5, 6, 7
DRTRY, QACK and TLBISYNC)
11a SYSCLK to address/data/transfer
attribute inputs invalid (input hold)
1.0
1.0
0
—
—
—
1.0
1.0
0
—
—
—
1.0
1.0
0
—
—
—
1.0
1.0
0
—
—
—
ns
ns
ns
2
3
11b SYSCLK to all other inputs invalid
(input hold)
11c HRESET to mode select inputs
invalid (input hold) (for DRTRY,
QACK, and TLBISYNC)
4, 6, 7
Notes:
1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4],
TC[0–1], TBST, TSIZ[0-2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table
must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
10
603e and EM603e Hardware Specification
IBM [ IBM ]
