1
Table 9. Output AC Timing Specifications (Continued)
Vdd = AVdd = 2.5 ± 5% Vdc (= 3.3 ± 5% Vdc for PID6). O Vdd = 3.3 ± 5% Vdc. GND = 0 Vdc, 0 ≤ Tj ≤ 105 °C. C = 50 pF (unless otherwise
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noted) (PID6 maximum timing specifications assume C = 50pF).
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PID6
PID7v
PID7t
80 MHz
100 MHz
166 MHz
200 MHz
Num
Characteristic
Unit Notes
Min Max Min Max Min Max Min Max
19 SYSCLK to ARTRY precharge enable
—
0.2 *
tsysclk
+ 1.0
—
0.2 *
tsysclk
+ 1.0
—
0.2 *
tsysclk
+ 1.0
—
ns
2,4,7
20 Maximum delay to ARTRY precharge
—
—
—
—
1.2
—
—
1.0
2.0
—
—
1.0 tsysclk 4,7
2.0 tsysclk 5,7
21 SYSCLK to ARTRY high impedance after
precharge
2.25
Notes:
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V)
of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. This minimum parameter assumes C = 0 pF.
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3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage
from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must
be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in
question.
5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk
.
7. Nominal precharge width for ARTRY is 1.0 tsysclk
.
603e and EM603e Hardware Specification
13
IBM [ IBM ]
