algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
•
Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
•
Integrated power management
— Low-power 3.3-volt design — PID6
— Low-power 2.5/3.3-volt design — PID7v and PID7t
— Internal processor/bus clock multiplier that provides 1.5, 2, 2.5, 3, 3.5, 4, and 1:1 @ 66MHz for
PID6, and 4, 4.5, 5, 5.5, and 6 for PID7
— Two power saving modes: doze and nap
— Automatic dynamic power reduction when internal functional units are idle
•
In-system testability and debugging features through JTAG boundary-scan capability.
1.3 General Parameters
Table 1 603e and EM603e General Parameters
Parameter
Technology
Die size
Transistor count
Logic design
PID6
0.5
µm
CMOS four-layer
metal
11.67 mm x 8.4 mm
(98mm
2
)
2.6 million
Fully-static
PID7v
0.35
µm
CMOS, five-layer
metal
10.5 mm x 7.5 mm
(79 mm
2
)
2.6 million
Fully-static
PID7t
0.35
µm
CMOS, five-layer
metal
10.5 mm x 7.5 mm
(79 mm
2
)
2.6 million
Fully-static
4
603e and EM603e Hardware Specification
IBM [ IBM ]
