The 603e and EM603e have a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e and
EM603e interface protocol allows multiple masters to compete for system resources through a central
external arbiter. The 603e and EM603e provide a three-state coherency protocol that supports the exclusive,
modified, and invalid cache states. This protocol is a compatible subset of the modified/exclusive/invalid
(MEI) three-state protocol and operates coherently in systems that contain three-state caches. The 603e and
EM603e support single-beat and burst data transfers for memory accesses, and supports memory-mapped
I/O.
The 603e and EM603e are offered in three versions:
1. PID6, which is a 3.3 V device
2. PID7v, which is a 2.5/3.3 V device
3. PID7t, which is a 2.5/3.3 V device.
All three maintain full interface compatibility with TTL devices. Each version is also offered with the
floating point unit fully tested and also without the floating point unit for those applications not needing
floating point.
1.2 Common Features
This section summarizes features of the 603e’s and EM603e’s implementation of the PowerPC architecture.
Major features of the 603e and EM603e are as follows:
•
High-performance, superscalar microprocessor
—
—
—
—
•
As many as three instructions issued and retired per clock
As many as five instructions in execution per clock
Single-cycle execution for most instructions
Pipelined FPU for all single-precision and most double-precision operations (the FPU is not
available on the EM603e)
Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations (the FPU is
not available on the EM603e)
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
•
High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
603e and EM603e Hardware Specification
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