Datasheet
Preliminary
CPC945 Bridge and Memory Controller
Table 4-17. CPC945 Bridge and Memory Controller Pin List by Grid Position (Page 3 of 12)
Grid Position
D36
E01
Signal Name
DDR_CS13
Grid Position
F01
Signal Name
Grid Position
G02
G03
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
K01
K02
K03
K04
Signal Name
PCIE_HSIP1
#GND
#VDD
#GND
PCIE_HSIN4
PCIE_HSIP0
PCIE_HSIN0
PCIE_HSIP6
PCIE_HSIN15
#VDD
F02
PCIE_HSOP4
PCIE_AV25_0
PCIE_AV25_1
PCIE_AVREG_1
PCIE_REFCLK_AVDD2
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_REFCLK_AVDDA
PCIE_REFCLK_AGNDA
PCIE_UCAL_RES1
HT_REFCLK_P
HT_REFCLK_N
HT_CAD_TXP2
HT_CAD_TXN2
HT_CLK_TXN0
HT_CLK_TXP0
HT_CTL_TXP0
HT_CTL_TXN0
HT_CAD_RXN13
HT_CAD_RXP13
HT_CAD_RXN6
HT_CAD_RXP6
HT_CTL_RXN0
#VD3
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
H01
H02
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
J01
PCIE_HSIN6
#VDD
#GND
PCIE_HSIN10
#VDD
PCIE_HSIP10
#GND
PCIE_AV25_2
#GND
PCIE_AVREG_2
#VDD
PCIE_HSIP12
#VDD
PCIE_HSIN12
#GND
HT_REFCLK_AVDD2
#GND
SYS_THDIO_G
#VD4
HT_CAD_TXP1
#VD4
HT_CAD_TXN1
#GND
HT_CAD_TXP4
#GND
HT_CAD_TXN4
#VD4
HT_CAD_TXP5
#VD4
HT_CAD_TXN5
#GND
HT_CAD_RXN10
#GND
HT_CAD_RXP10
#VDD
HT_CAD_RXP3
#VDD
HT_CAD_RXN3
#GND
HT_CAD_RXP5
#GND
HT_CAD_RXN5
#VD3
#GND
#GND
#VD3
DDR_CS14
#GND
DDR_DQ100
DDR_DQ102
DDR_DQSN12
DDR_DQSP12
DDR_DQ103
DDR_CS12
DDR_DQ101
PCIE_HSON1
PCIE_HSOP1
PCIE_HSOP5
DDR_DQ97
#GND
DDR_DQ98
#VD3
#VD3
DDR_DQ99
#GND
#GND
DDR_DQ96
#VD3
#VD3
#GND
#GND
#VD2
#VDD
J02
PI0_ADI43
#GND
J03
#GND
A15-6009-03
December 18, 2007 - IBM Confidential
Page 59 of 69
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