Datasheet
CPC945 Bridge and Memory Controller
Preliminary
Table 4-17. CPC945 Bridge and Memory Controller Pin List by Grid Position (Page 2 of 12)
Grid Position
A35
A36
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
Signal Name
Grid Position
B35
B36
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
Signal Name
DDR_DQ104
Grid Position
C35
C36
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
G01
Signal Name
depop
depop
#VDD
#GND
#VD3
depop
#GND
PCIE_HSIP4
PCIE_HSOP0
PCIE_AVREG_0
PCIE_HSIN7
#VDD
PCIE_HSON4
#GND
PCIE_HSON0
#VDD
#VDD
#GND
PCIE_HSIP7
#GND
PCIE_HSIP15
PCIE_HSIP11
PCIE_HSIN11
PCIE_HSOP10
PCIE_HSON10
PCIE_HSIN9
PCIE_HSIP9
PCIE_HSIP14
#GND
PCIE_HSIN14
#VDD
PCIE_HSOP14
#VDD
PCIE_HSON14
#GND
PCIE_HSIP8
#GND
PCIE_HSIN8
#VDD
PCIE_HSOP12
#VDD
PCIE_UCAL_RES0
SYS_THDIO_D
HT_CAD_TXN0
HT_CAD_TXP0
HT_CAD_TXN3
HT_CAD_TXP3
HT_CAD_TXP6
HT_CAD_TXN6
HT_CLK_RXN1
HT_CLK_RXP1
HT_CAD_RXP1
HT_CAD_RXN1
HT_CAD_RXN0
HT_CAD_RXP0
DDR_VREF_14_15
DDR_DQ121
PCIE_HSON12
#GND
HT_CTL_TXP1
#GND
HT_CTL_TXN1
#VD4
HT_CAD_TXP9
#VD4
HT_CAD_TXN9
#GND
HT_CAD_TXP8
#GND
HT_CAD_TXN8
#VD4
HT_CTL_RXP1
#VDD
HT_CTL_RXN1
#GND
HT_CAD_RXN8
#GND
HT_CAD_RXP8
#VDD
HT_CLK_RXN0
#VDD
HT_CLK_RXP0
#GND
DDR_CS15
#GND
DDR_DQ120
#VD3
DDR_DQ122
#VD3
DDR_DQ115
DDR_DQ123
#GND
DDR_DQ105
DDR_DQ113
#GND
DDR_DQSN13
DDR_DQSP13
DDR_DQ107
DDR_DQ112
#VD3
#VD3
#GND
DDR_DQ111
#GND
DDR_DQ139
DDR_DQ109
DDR_DQ110
DDR_DQ136
#VD3
PCIE_HSIN1
A15-6009-03
December 18, 2007 - IBM Confidential
Page 58 of 69
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