CPC945 Bridge and Memory Controller
Preliminary
Datasheet
Revision Log
Each release of this document supersedes all previously released versions. The revision log lists all signifi-
cant changes made to the document since its initial release. In the rest of the document, change bars in the
margin indicate that the adjacent text was modified from the previous release of this document.
Revision Date
Contents of Modification
A15-6009-03.
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Changed PowerPC 970 to PowerPC 970xx throughout document.
Added 970FX processor support to Features on page 13.
Removed DD 1.0, DD 1.1, and added DD 2.0 to Table 1-1 CPC945 Revision Register on page 14.
Revised Figure 1-1 Part Number Legend on page 14.
Updated design revision level, package type, junction temperature range, and processor sort in Figure
1-1 Part Number Legend on page 14.
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Removed speed classification column and updated Table 1-2 CPC945 Standard OEM Sort Speed Bins
for DD 1.2 on page 15.
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Added Table 1-3 CPC945 Standard OEM Sort Speed Bins for DD 2.0 on page 15.
Revised Table 2-1 General Parameters of the CPC945 on page 19.
Added Table 2-2 Allowable Forces on the CPC945 Package on page 20 and Figure 2-2 Force Diagram
for the CPC945 Package on page 20.
December 18, 2007
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Added note 3 to Table 3-1 Absolute Maximum Ratings on page 21.
Updated VDD2, PDD, PDD4, and PT parameters in Table 3-4 Recommended Functional dc Operating
Ratings on page 23.
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Revised Section 3.6 Processor Interface Specifications on page 29.
Revised HT_CLK_TXN[0:1] and HT_CLK_TXP[0:1] definitions (see Table 4-4 HyperTransport Signal
Pins on page 38).
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Added pull-up resistor recommendation to Table 4-4 HyperTransport Signal Pins on page 38, Table 4-7
Processor Interface Support Signal Pins on page 40, Table 4-9 System Support Signal Pins on
page 41, and Table 4-10 I2C Signal Pins on page 41.
Added overbar to IRQ[0:3] signals in Table 4-9 System Support Signal Pins on page 41, Table 4-16
CPC945 Bridge and Memory Controller Pin List by Signal Name on page 45, and Table 4-17 CPC945
Bridge and Memory Controller Pin List by Grid Position on page 57.
Revised OBSV signal definition (see Table 4-12 JTAG and Test Support Signal Pins on page 42).
A15-6009-02.
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Corrected ferrite bead part number in Figure 3-2 Analog VDD Filtering for the Processor Interface and
DDR2 Interface Phase-Locked Loops on page 24.
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Edited Section 2.1.2 PCI Express Interface on page 18.
Added missing signal pin (#VD2 at AM07) to Table 4-16 CPC945 Bridge and Memory Controller Pin
List by Signal Name on page 45.
August 24, 2006
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Edited Table 2-1 General Parameters of the CPC945 on page 19.
Edited Figure 3-4 Typical External Termination for LVDS Input and Figure 3-5 Typical External Termina-
tion for CMOS Oscillator on page 28.
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Added additional note to Figure 3-4 Recommended Functional dc Operating Ratings on page 23.
Updated Figure 4-1 CPC945 Signal Pin Overview on page 35.
A15-6009-01.
August 15, 2006
August 4, 2006
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DD2 operational voltage range changed to 1.3 V - 1.5 V range.
VDD2 minimum voltage changed from 1.1 V to 1.25 V.
Document number changed to A15-6009-00.
A15-6009-03
December 18, 2007
Revision Log
Page 9 of 69
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