Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Features
• Up to 133MHz PowerPC 60x 64-bit bus
• 2.5V 60x PowerPC bus
• Supports 100- and 133-MHz SDRAM including PC100 and PC133
• Up to 2MB Flash Boot ROM support
• 32-bit 33MHz/64-bit 33-66MHz asynchronous dual PCI buses
• Bidirectional interface to two external 32-bit registers
• PreP and CHRP compliant design
• One-channel chained DMA controller
• Up to 256-MB Extended Flash support
• 32-bit PCI bus has 3.3V, 5V-tolerant I/O
• 64-bit PCI bus has 3.3V I/O
• Power dissipation estimate of 2.1W at 133MHz
• PLL to reduce on-chip system clock skew
• JTAG controller
60x Bus Interface
• Supports 740L/750L, 750CX/Cxe, or 74xx PowerPC
• Up 133-MHz external bus operation
• Supports four processors
• 64-bit data bus with 8 bits of parity
• 32-bit address bus with 4 bits of parity
• Dual 32-byte store back buffers
• High bandwidth, 4-way arbiter
• Little Endian mode PowerPC
• Supports SYNC/EIEIO ordering operations
• Supports L2 cache or bus slaves with external decode
SDRAM Memory Controller
The CPC710 Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported.
Features include:
• Support for 100- and 133-MHz SDRAM including PC100 and PC133 and Registered DIMMs
• Supports 16-, 64-, 128-, and 256-Mbit SDRAMs
• Up to 3.5GB addressing range using 16-, 64-,128-, 256-, 512- or 1024-MB DIMMs
• 2-way interleaved SDRAM with ECC (external MUX to reduce pin count)
• Programmable timing parameters
• Up to 6 dual bank DIMMs
• Up to 4 banks supported for Multibanking
• SDRAM Access command queue with look ahead override option for CPU, PCIs, and DMA
• Access based on 32-byte cache line reload
• Three separate dual 32-byte load buffers (PCI-32, PCI-64, 60x)
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IBM [ IBM ]
