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IBM25CPC710CF3A100 参数 Datasheet PDF下载

IBM25CPC710CF3A100图片预览
型号: IBM25CPC710CF3A100
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA728, 35 MM, PLASTIC, FLIP CHIP, BGA-728]
分类和应用: PC外围集成电路
文件页数/大小: 54 页 / 430 K
品牌: IBM [ IBM ]
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Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Features
• IBM CPC710 PowerPC
to PCI bridge
- 2.5V PPC60x processor bus running at up
to 133MHz
- Dual 32- and 64-bit PCI interfaces
- 100- and 133-MHz SDRAM interface
- Internal DMA controller
- 2-MB Flash boot ROM support
- 256-MB Extended Flash support
- JTAG for board level testing
• PCI interfaces
- Two independent bridges with parking
- PCI Revision 2.1 compliant
- 3.3V signal interface
• Synchronous DRAM (SDRAM) interface
operating at 100 or 133MHz
- Support for PC100 and PC133 SDRAM and
Registered DIMMs
• PPC60x Bus interface
- Up to 133MHz bus
- One to four processors
- Up to 6 outstanding transaction requests
- Little Endian mode available
• System I/O interface
- 2-MB Flash Boot ROM
- 256-MB Extended Flash
• DMA controller
- Single channel
- System memory-to-PCI transfers only
- Store-gather for enhanced performance
- Two-way interleaved operation with ECC
using external multiplexer
- Up to 3.5GB addressing space using 16-,
64-,128-, 256-, 512- or 1024-MB DIMMs
Description
The CPC710 IBM PCI Bridge and Memory
Controller is a highly integrated host bridge device
that interfaces PowerPC 60x buses to SDRAM-
based system memory and also provides two PCI
interfaces. It supports up to four processors with
pipelining for up to six outstanding transaction
requests.
The memory controller supports SDRAM, allowing
the memory to burst data on most bus cycles at
100MHz or 133MHz.
For system designs requiring high I/O bandwidth,
there are two PCI host bus bridges. One bridge
supports a standard 32-bit, 33MHz PCI bus, while
the other supports 64 bits at up to 66MHz for
graphics and high speed communications.
An internal DMA controller allows high speed data
transfer between Memory and I/O. Store-gathering
enhances the CPU-to-I/O performance.
Technology: IBM CMOS SA-12E, 0.25
µ
m
Package: 35mm, 728-ball flip chip-plastic ball grid
array (FC-PBGA)
Power (estimated): Typical 2.1W, Maximum 2.6W
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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