Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
PCI Bridges
• Two independent PCI bus bridges with parking
• PCI revision 2.1 compliant
• PCI-32 with 3.3V, 5V tolerant interface
• PCI-64 with 3.3 V interface
• Buses run asynchronously to processor and memory controller
• External arbitration available for both buses
• Dual 32-byte buffers in each PCI bridge
• Round-robin PCI arbiter
• Coherency for memory access through DMA controller or through PCI master
JTAG
• IEEE 1149.1 Test Access Port (TAP)
• IBM RISCWatch Debugger support
6