Discontinued (9/98 - last order; 3/99 last ship)
IBM11T8645HP
8M x 64 144 PIN SO DIMM
Refresh Cycle
-50
-60
Symbol
Parameter
Unit
Notes
Min
—
Max
5
Min
—
Max
5
CAS Setup Time
tCSR
ns
ns
ns
ns
(CAS before RAS Refresh Cycle)
CAS Hold Time
tCHR
tWRP
tWRH
—
—
—
5
5
5
—
—
—
10
10
10
(CAS before RAS Refresh Cycle)
WE Setup Time
(CAS before RAS Refresh Cycle)
WE Hold Time
(CAS before RAS Refresh Cycle)
tRPC
tREF
RAS Precharge to CAS Hold Time
Refresh Period
—
—
5
—
—
5
ns
128
128
ms
1
1. 4096 refreshes are required every 128ms.
Self Refresh Cycle
-50
-60
Symbol
Parameter
Unit
Notes
Min
100
Max
—
Min
100
Max
—
RAS Pulse Width
tRASS
tRPS
tCHS
µs
ns
ns
1
1
1
During Self Refresh Cycle
RAS Precharge Time
During Self Refresh Cycle
84
—
—
104
-50
—
—
CAS Hold Time
During Self Refresh Cycle
-50
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row
addresses are being refreshed in an EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only
one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other
manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed imme-
diately before entry to and immediately after exit from Self Refresh.
©IBM Corporation. rights reserved.
Use is further subject to the provisions at the end of this document.
75H3164
GA14-4479-02
Rev 11/97
Page 12 of 32
IBM [ IBM ]
