Discontinued (9/98 - last order; 3/99 last ship)
IBM11T8645HP
8M x 64 144 PIN SO DIMM
Presence Detect Read and Write Cycle
-70
Symbol
Parameter
Unit
Notes
Min
Max
80
fSCL
TI
SCL Clock Frequency
kHZ
ns
µs
µs
µs
µs
µs
µs
µs
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
100
7.0
tAA
0.3
6.7
4.5
6.7
4.5
6.7
0
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
Clock Low Period
Clock High Period
Start Condition Setup Time(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
500
ns
µs
ns
µs
ns
ms
SDA and SCL Rise Time
1
tf
SDA and SCL Fall Time
300
tSU:STO
tDH
Stop Condition Setup Time
6.7
Data Out Hold Time
300
tWR
Write Cycle Time
15
1
1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H3164
GA14-4479-02
Rev 11/97
Page 13 of 32
IBM [ IBM ]
