IBM11N16845BB
IBM11N16845CB
Preliminary
16M x 72 Super EOS Module
Refresh Cycle
-6R
Symbol
Parameter
Unit
Notes
Min
10
Max
—
CAS Hold Time
(CAS before RAS Refresh Cycle)
tCHR
tCSR
tWRP
ns
ns
ns
ns
CAS Setup Time
(CAS before RAS Refresh Cycle)
5
—
—
—
WE Setup Time
(CAS before RAS Refresh Cycle)
10
10
WE Hold Time
(CAS before RAS Refresh Cycle)
tWRH
tRPC
RAS Precharge to CAS Hold Time
5
—
64
64
ns
ms
ms
13/11 addressing
12/12 addressing
—
—
1
2
tREF
Refresh Period
1. 8192 refreshes are required every 64ms (13/11 addressing) for ROR; 4096 refreshes are required every 64ms for CBR.
2. 4096 refreshes are required every 64ms (12/12 addressing) for ROR or CBR.
Presence Detect Read and Write Cycle
Symbol
fSCL
Parameter
Min
Max
100
100
3.5
Unit
kHZ
ns
Notes
SCL Clock Frequency
TI
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
tAA
µs
µs
µs
µs
µs
µs
µs
ns
0.3
4.7
4.0
4.7
4.0
4.7
0
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
Clock Low Period
Clock High Period
Start Condition Setup Time(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
250
µs
ns
SDA and SCL Rise Time
1
tf
SDA and SCL Fall Time
300
tSU:STO
tDH
µs
ns
Stop Condition Setup Time
4.7
Data Out Hold Time
300
tWR
Write Cycle Time
15
ms
1
1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up
resistor, and the device does not respond to its slave address.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
75H5487
GA14-4642-00
Revised 11/96
Page 11 of 28
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