IBM11M4735CB-60T 参数 Datasheet PDF下载

Discontinued (9/98 - last order; 3/99 - last ship)

IBM11M4735C

IBM11M4735CB

4M x 72 DRAM Module

DC Electrical Characteristics

Symbol

I

CC1

(T

A

= 0 to +70°C, V

CC

= 3.3V

±

0.3V or V

CC

= 5.0V

±

0.5V)

Parameter

Min.

-50

-60

—

—

—

-50

-60

-50

-60

—

—

—

—

—

-50

-60

All but RAS

RAS

—

—

-10

-90

-10

Max.

1530

1350

36

1530

1350

1530

1170

18

1530

1350

+10

+90

+10

mA

1, 3

mA

1, 2, 3

mA

1, 3

mA

1, 2, 3

Units

Notes

Operating Current

Average Power Supply Operating Current

(RAS, CAS, Address Cycling: t

RC

= t

RC

min.)

Standby Current (TTL)

Power Supply Standby Current

(RAS = CAS = V

IH

)

RAS Only Refresh Current

Average Power Supply Current, RAS Only Mode

(RAS Cycling, CAS = V

IH

: t

RC

= t

RC

min)

EDO Page Mode Current

Average Power Supply Current, EDO Page Mode

(RAS = V

IL

, CAS, Address Cycling: t

HPC

= t

HPC

min)

Standby Current (CMOS)

Power Supply Standby Current

(RAS = CAS = V

CC

- 0.2V)

CAS Before RAS Refresh Current

Average Power Supply Current, CAS Before RAS Mode

(RAS, CAS, Cycling: t

RC

= t

RC

min)

Input Leakage Current

Input Leakage Current, any input

(0.0

≤

V

IN

≤

(V

CC

+ 0.3V)), All Other Pins Not Under Test = 0V

Output Leakage Current

(D

OUT

is disabled, 0.0

≤

V

OUT

≤

V

CC

)

Output Level (TTL)

Output “H” Level Voltage

(I

OUT

= -2.5mA for 3.3V, or I

OUT

= -5mA for 5.0V)

Output Level (TTL)

Output “L” Level Voltage

(I

OUT

= +2.1mA for 3.3V, or I

OUT

= +4.2mA for 5.0V)

I

CC2

mA

I

CC3

I

CC4

I

CC5

mA

I

CC6

I

I(L)

I

O(L)

V

OH

µA

µA

2.4

V

CC

V

V

OL

0.0

0.4

V

1. I

CC1

, I

CC3

, I

CC4

, and I

CC6

depend on cycle rate.

2. I

CC1

and I

CC4

depend on output loading. Specified values are obtained with the output open.

3. Address can be changed once or less while RAS =V

IL

. In the case of I

CC4

, it can be changed once or less when CAS =V

IH

.

AC Characteristics

(T

A

= 0 to +70°C, VCC = 3.3V

±

0.3V or 5.0V

±

0.5V)

1. V

IH

(min) and V

IL

(max) are reference levels for measuring timing of input signals. Transition times are measured between V

IH

and

V

IL

.

2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is

achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh

cycles is required.

3. The specified timings include buffer, loading, and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the

DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specifications of 50ns and

60ns.

4. AC measurements assume t

T

= 2ns.

©IBM Corporation. All rights reserved.

Use is further subject to the provisions at the end of this document.

50H4201.E20982E

Revised 8/98

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