Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M4735C
IBM11M4735CB
4M x 72 DRAM Module
Truth Table
Row
Column
Function
RAS
CAS
WE
OE
PDE
DQx
Address Address
H→X
Standby
Read
H
L
L
L
X
H
X
L
X
X
X
X
X
X
High Impedance
Valid Data Out
Valid Data In
L
L
L
Row
Row
Row
Col
Col
Col
Early-Write
Late-Write
L
X
H
H→L
Valid Data In
Valid Data Out,
Valid Data In
H→L
L→H
RMW
L
L
Row
Col
X
EDO Page Mode - Read
1st Cycle
H→L
H→L
H→L
H→L
H→L
L
L
L
L
L
H
H
L
L
Row
N/A
Col
Col
Col
Col
Col
X
X
X
X
X
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
Subsequent Cycles
EDO Page Mode - Write
1st Cycle
L
X
Row
N/A
Subsequent Cycles
L
X
EDO Page Mode - RMW
1st Cycle
Valid Data Out,
Valid Data In
H→L
L→H
Row
Valid Data Out,
Valid Data In
H→L
H→L
L→H
Subsequent Cycles
L
N/A
Col
X
L
H
L
L
L
X
H
H
H
X
X
L
Row
X
N/A
X
X
X
X
X
High Impedance
High Impedance
Data Out
RAS-Only Refresh
H→L
CAS-Before-RAS Refresh
L→H→L
L→H→L
Read
Write
Row
Row
Col
Col
Hidden Refresh
X
Data In
Not Affected
(PD Bits Valid)
Read Presence Detects
X
X
X
X
X
X
L
Presence Detect
Pin
-50
1
-60
1
PD1 (PD1 - PD4: Addressing/Density)
PD2
1
1
PD3
0
0
PD4
1
1
PD5 (EDO Detection)
PD6 (PD6 - PD7: Speed)
PD7
1
1
0
1
0
1
PD8 (Parity/ECC Designator)
ID0 (DIMM Type/Width)
ID1 (Refresh Mode)
0
0
0
0
0
0
1. PD1-8 are buffered outputs (0 = driven to V , 1 = open)
OL
2. ID0-1 are unbuffered outputs (0 = V , 1 = open)
SS
3. PDE should be tied high or low at system level if not used
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4201.E20982E
Revised 8/98
Page 4 of 30
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