Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
IBM11M4735C
IBM11M4735CB
4M x 72 DRAM Module
Features
• 168-Pin JEDEC-Standard 8-Byte Dual In-Line
Memory Module
• 4Mx72 Extended Data Out Page Mode DIMM
• Performance:
-50
t
RAC
RAS Access Time
t
CAC
CAS Access Time
t
AA
t
RC
Access Time From Address
Cycle Time
50ns
18ns
30ns
89ns
20ns
-60
60ns
20ns
35ns
104ns
25ns
• Optimized for ECC applications
• System Performance Benefits:
- Buffered inputs (except RAS, Data)
- Reduced noise (32 V
SS
/V
CC
pins)
- 4-Byte Interleave enabled
- Buffered PDs
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
• 4096 refresh cycles distributed across 64ms
• 12/10 addressing (Row/Column)
• Card sizes: 5.25" x 1.0" x 0.354" (SOJ)
5.25" x 1.0" x 0.175" (TSOP)
• DRAM
S
in SOJ or TSOP Package
t
HPC
EDO Mode Cycle Time
• Inputs and outputs are LVTTL (3.3V) or TTL
(5.0V) compatible
• Single 3.3V
±
0.3V or 5.0V
±
0.5V Power Supply
• Gold contacts
Description
IBM11M4735C is an industry-standard 168-pin
8-byte Dual In-Line Memory Module (DIMM) which
is organized as a 4Mx72 high-speed memory array
designed with EDO DRAMs for ECC applications.
The DIMM uses 18 4Mx4 EDO DRAMs in SOJ or
TSOP packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 20ns for 50ns DRAM modules.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and
RAS
signals are not
buffered, which preserves the DRAM access specifi-
cations of 50ns and 60ns.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance, and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, the system
will determine that ECC DIMMs are installed if PD8
is low (0). ID0 need not be sensed since both x72
and x80 ECC DIMMs will function in a x72 bank.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x64 non-parity
DIMMs and the ECC DIMMs (5V and 3.3V).
Card Outline 3.3V
Detail A
(Front)
(Back)
1
85
10 11
94 95
40 41
124 125
See Detail A
for 5.0V Version
84
168
50H4201.E20982E
Revised 8/98
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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