Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M4735C
IBM11M4735CB
4M x 72 DRAM Module
Write Cycle (Late Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
CAS
tCAS
VIL
tRAD
tASR
tASC
tRAH
tCAH
VIH
Address
Row
tWRP
Column
VIL
tWRH
tRCS
tCWL
VIH
VIL
tWP
NOTE 1
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tODD
tDZO
tDS
tWRP
tDZC
VIH
VIL
DIN
Hi-Z
Valid Data In
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
t
OEH greater than or equal to tCWL
: “H” or “L”
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4201.E20982E
Revised 8/98
Page 14 of 30
IBM [ IBM ]
