Discontinued (9/98 - last order; 3/99 - last ship)
IBM11M4735C
IBM11M4735CB
4M x 72 DRAM Module
Read-Modify-Write-Cycle
tRWC
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tCRP
tRCD
tRSH
VIH
VIL
tCAS
tRAD
tASR
tASC
tRAH
tCAH
VIH
VIL
Address
Row
Column
tCWD
tRWL
tCWL
tAWD
tWRH
tWRP
tRWD
tWP
VIH
VIL
NOTE 1
tAA
WE
OE
tRCS
tOEH
VIH
VIL
tOEA
tDZC
tDH
tDS
tDZO
VIH
VIL
DIN
Hi-Z
tCAC
DIN
tODD
tCLZ
tOEZ
VOH
VOL
*
Hi-Z
Hi-Z
DOUT
DOUT
*
tRAC
tOEH greater than or equal to tCWL
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4201.E20982E
Revised 8/98
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