IBM11M4730H
IBM11M4730HB
4M x 72 DRAM MODULE
AC Characteristics
(TA = 0 to +70°C, Vcc = 3.3V
±
0.3V or 5.0V
±
0.5V)
1. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and
V
IL
.
2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the
Dram device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specifications of 60ns and
70ns.
4. AC measurements assume t
T
= 5ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles
Symbol
t
RC
t
RP
t
CP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ODD
t
DZO
t
DZC
t
AR
t
T
Parameter
(Common Parameters)
-60
Min
Max
—
—
—
10K
10K
—
—
—
—
40
25
—
—
—
—
—
—
—
30
Min
130
50
10
70
20
5
8
2
10
18
13
25
68
10
25
-2
-2
—
3
-70
Unit
Max
—
—
—
10K
10K
—
—
—
—
45
30
—
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
4
5
5
6
2
3
1
110
40
10
60
15
5
8
2
10
18
13
20
58
10
20
-2
-2
—
3
Notes
Random Read or Write Cycle Time
RAS Precharge Time
CAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
OE to D
IN
Delay Time
OE Delay Time from D
IN
CAS Delay Time from D
IN
Column Address Hold Time Referenced to RAS
Transition Time (Rise and Fall)
1. The minimum t
CAS
requires t
CSH
to be met for both writes and reads. Also, because of the buffer, the minimum t
CAS
for a read cycle
must be extended to guarantee the data out window (t
OH
) in the application. For example, a t
CAS
of 15ns plus a minimum t
OH
of 2ns
would result in turning data out of the DIMM at 17ns (3ns before max t
CAC
of 20ns).
2. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. The t
RCD
(max) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC.
3. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. The t
RAD
(max) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA.
4. Either t
CDD
or t
ODD
must be satisfied.
5. Either t
DZC
or t
DZO
must be satisfied.
6. This timing parameter is not applicable to this product, but applies to a related product in this family.
54H8529
SA14-4637-01
Released 3/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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