IBM0625404GT3B IBM0625164GT3B
IBM0625804GT3B IBM06254B4GT3B
256Mb Double Data Rate Synchronous DRAM
Advance
Power-Down
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down
mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power-
down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur
before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be
maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, power-
down duration is limited by the refresh requirements of the device, so in most applications, the self refresh
mode is preferred over the DLL-disabled power-down mode.
The power-down state is synchronously exited when CKE is registered HIGH (along with a Nop or Deselect
command). A valid, executable command may be applied one clock cycle later.
Power Down
CK
CK
t
t
IS
IS
CKE
Command
VALID
NOP
VALID
NOP
No column
access in
progress
Exit
power down
mode
Don’t Care
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997
10/99
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