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IBM0612804GT3B-8N 参数 Datasheet PDF下载

IBM0612804GT3B-8N图片预览
型号: IBM0612804GT3B-8N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX8, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1362 K
品牌: IBM [ IBM ]
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V
DD  
* VTT is not applied directly to the device, however tVTD must be  
greater than or equal to zero to avoid device latchup.  
V
DDQ  
** tMRD is required before any command can be applied and  
200 cycles of CK are required before a Read command can be applied.  
t
VTD  
The two Autorefresh commands may be moved to follow the first MRS,  
but precede the second Precharge All command.  
V
(System*)  
TT  
V
REF  
t
CK  
200 cycles of CK**  
t
CH  
t
t
t
t
t
t
MRD  
200µs  
MRD  
MRD  
RP  
RFC  
RFC  
t
CL  
CK  
CK  
t
t
IH  
t
t
IS  
IS  
LVCMOS LOW LEVEL  
CKE  
IH  
NOP  
PRE  
EMRS  
MRS  
PRE  
AR  
AR  
MRS  
ACT  
Command  
DM  
t
IH  
t
IS  
CODE  
CODE  
CODE  
CODE  
CODE  
RA  
RA  
BA  
A0-A9, A11  
A10  
t
t
t
IH  
IH  
IH  
t
t
t
IS  
IS  
IS  
CODE  
ALL BANKS  
ALL BANKS  
t
IH  
t
IS  
BA0=L  
BA1=L  
BA0=L  
BA1=L  
BA0=H  
BA1=L  
BA0, BA1  
DQS  
High-Z  
High-Z  
DQ  
Power-up:  
DD and CK  
stable  
Extended Mode  
Register Set  
Load Mode  
Register, Reset DLL  
Load Mode  
Register  
(with A8 = L)  
Don’t Care  
V
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