Preliminary
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Recommended DC Operating Conditions
(T
A
= 0 to +85°C)
Parameter
Supply Voltage
Output Driver Supply Voltage
Input High Voltage
Input Low Voltage
Input Reference Voltage
Clocks Signal Voltage
Differential Clocks Signal Voltage
Clocks Common Mode Voltage
1.
2.
3.
4.
5.
6.
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
REF
V
IN - CLK
V
DIF - CLK
V
CM - CLK
Min.
2.5 - 5%
1.4
V
REF
+0.1
-0.3
0.68
-0.3
0.1
0.55
Typ.
2.5
1.5, 1.8
—
—
0.90
—
—
—
Max.
2.5 + 5%
1.9
V
DDQ
+ 0.3
V
REF
- 0.1
0.95
V
DDQ
+ 0.3
V
DDQ
+ 0.6
0.90
Units
V
V
V
V
V
V
V
V
Notes
1
1
1, 2
1, 3
1, 6
1, 4
1, 5
1
All voltages referenced to V
SS
. All V
DD
, V
DDQ
, and V
SS
pins must be connected.
V
IH
(Max)DC = V
DDQ
+ 0.3 V, V
IH
(Max)AC = V
DDQ
+ 0.85 V (pulse width
≤
4.0ns).
V
IL
(Min)DC = -0.3 V, V
IL
(Min)AC = -1.5 V (pulse width
≤
4.0ns).
V
IN-CLK
specifies the maximum allowable DC excursions of each differential clock (K, K).
V
DIF-CLK
specifies the minimum Clock differential voltage required for switching.
Peak to Peak AC component superimposed on V
REF
may not exceed 5% of V
REF.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 25
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