IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
Preliminary
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os
and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the
RAM core.
In conformance with IEEE Std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary
Scan register, Bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST
signal is not required.
Signal List
• TCK: Test Clock
• TMS: Test Mode Select
• TDI: Test Data In
• TDO: Test Data Out.
JTAG DC Operating Characteristics (TA = 0 to +85°C)
Operates with JEDEC Standard 8-5 (2.5V) logic signal levels
Parameter
JTAG Input High Voltage
Symbol
Min.
1.7
-0.3
2.1
—
Typ.
—
Max.
+0.3
Units
Notes
1
V
V
V
V
V
V
IH1
DD
V
1
JTAG Input Low Voltage
JTAG Output High Level
JTAG Output Low Level
—
0.8
IL1
V
1, 2
1, 3
—
—
OH1
V
—
0.2
OL1
1. All JTAG inputs and outputs are LVTTL compatible only.
2. I
≥ -|2mA|
OH1
OL1
3. I
≥ +|2mA|.
JTAG AC Test Conditions (TA = 0 to +85°C, VDD = 2.5V -5%, +5%)
Parameter
Input Pulse High Level
Symbol
Conditions
3.0
Units
V
V
IH1
V
Input Pulse Low Level
0.0
V
IL1
T
Input Rise Time
2.0
ns
ns
V
R1
T
Input Fall Time
2.0
F1
Input and Output Timing Reference Level
1.25
crrh2519.07
©IBM Corporation. All rights reserved.
12/13/00
Use is further subject to the provisions at the end of this document.
Page 15 of 25
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