IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Read and Deselect Cycles Timing Diagram
t
KLKH
t
t
KHKH
KHKL
K
t
AVKH
A1
A2
A3
A3
A4
SA
SS
SW
G
t
KHAX
t
KHSX
t
SVKH
t
WVKH
t
t
GLQV
KHWX
t
GHQZ
t
t
KHQX
KHQZ
Q4
DQ
Q1
Q3
Q2
t
t
t
KHQV
t
GLQX
KHQX4
KHQV
crrh2519.07
12/13/00
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Use is further subject to the provisions at the end of this document.
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