IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
Preliminary
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Read Write Cycles Timing Diagram
t
KLKH
t
KHKL
t
KHKH
K
t
AVKH
A2
A1
A3
A2
SA
SS
A4
t
SVKH
t
KHAX
t
KHSX
t
t
KHWX
t
KHWX
SW
t
WVKH
t
WVKH
KHWX
t
KHWX
SBW
t
WVKH
t
WVKH
G
t
t
GHQZ
KHQV
t
KHQZ
t
KHDX
Q2
D4
Q3
Q1
D2
DQ
t
DVKH
t
t
KHQX4
KHQV
t
t
DVKH
KHDX
Notes:
1. D2 is the input data written in memory location A2.
2. Q2 is output data read from the write buffer, as a result of address A2 being a match
from the last write cycle address.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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