IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Instruction Set
Code
000
001
010
011
100
101
110
111
Instruction
SAMPLE-Z
IDCODE
Notes
1, 2
1, 2
5
SAMPLE-Z
PRIVATE
SAMPLE
PRIVATE
PRIVATE
BYPASS
4
5
5
3
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to V when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
SS
TDI when exiting the Shift DR state.
4. SAMPLE instruction does not place DQs in High-Z.
5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.
List of IEEE 1149.1 Standard Violations
• 7.2.1.b, e
• 7.7.1.a-f
• 10.1.1.b, e
• 10.7.1.a-d
• 6.1.1.d
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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