IBM043611QLAB
IBM041811QLAB
Preliminary
32K X 36 & 64K X 18 SRAM
IEEE 1149.1 TAP AND BOUNDARY SCAN
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os
and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the
RAM core.
In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary
Scan register, Bypass register and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST
signal is not required.
Signal List
• TCK: Test Clock
• TMS: Test Mode Select
• TDI: Test Data In
• TDO: Test Data Out
Caution: TCK, TMS, TDI inputs must be biased to a valid logic level, even if JTAG is not used.
JTAG Recommended DC Operating Conditions (T =0 to 70°C)
A
Parameter
Symbol
VIH1
Min.
2.2
-0.3
2.4
—
Typ.
—
Max.
VDD+0.3
0.8
Units
Notes
1
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Level
JTAG Output Low Level
V
V
V
V
VIL1
—
1
VOH1
VOL1
—
—
1, 2
1, 3
—
0.4
1. All JTAG Inputs/Outputs are LVTTL Compatible only.
2. IOH1 = -8mA at 2.4V.
3. IOL1 = +8mA at 0.4V.
JTAG AC Test Conditions (T =0 to +70°C, V =3.3 -5% + 10% V)
A
DD
Symbol
Parameter
Conditions
Units
V
Notes
VIH1
VIL1
TR1
TF1
Input Pulse High Level
Input Pulse Low Level
Input Rise Time
3.0
0.0
2.0
2.0
1.5
V
ns
ns
V
Input Fall Time
Input and Output Timing Reference Level
1. See AC Test Loading on page 8.
1
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
03H9040
SA14-4659-04
Revised 7/96
Page 13 of 21
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