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IBM041811QLAB-7 参数 Datasheet PDF下载

IBM041811QLAB-7图片预览
型号: IBM041811QLAB-7
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX18, 3.5ns, CMOS, PBGA119, BGA-119]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 21 页 / 301 K
品牌: IBM [ IBM ]
 浏览型号IBM041811QLAB-7的Datasheet PDF文件第11页浏览型号IBM041811QLAB-7的Datasheet PDF文件第12页浏览型号IBM041811QLAB-7的Datasheet PDF文件第13页浏览型号IBM041811QLAB-7的Datasheet PDF文件第14页浏览型号IBM041811QLAB-7的Datasheet PDF文件第16页浏览型号IBM041811QLAB-7的Datasheet PDF文件第17页浏览型号IBM041811QLAB-7的Datasheet PDF文件第18页浏览型号IBM041811QLAB-7的Datasheet PDF文件第19页  
IBM043611QLAB  
IBM041811QLAB  
Preliminary  
32K X 36 & 64K X 18 SRAM  
Scan Register Definition  
Register Name  
Bit Size X18  
Bit Size X36  
Instruction  
3
1
3
1
Bypass  
ID  
Boundary Scan *  
32  
51  
32  
70  
* The Boundary Scan chain consists of the following bits:  
36 or 18 bits for Data Inputs Depending on X18 or X36 Configuration  
15 bits for SA0 - SA14 for X36, 16 bits for SA0 - SA15 for X18  
4 bits for SBWa - SBWd in X36, 2 bits for SBWa and SBWb in X18  
9 bits for K, K, ZQ, SS, G, SW, ZZ, M1 and M2  
6 bits for Place Holders  
* K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used  
for Boundary Scan sampling.  
ID Register Definition  
Field Bit Number and Description  
Revision Number  
(31:28)  
Device Density and  
Configuration (27:18)  
Vendor Definition  
(17:12)  
Manufacture JEDEC  
Code (11:1)  
Start  
Bit(0)  
Part  
64K X18  
32K X36  
0000  
0000  
001 000 0011  
000 110 0100  
000101  
000101  
000 101 001 00  
000 101 001 00  
1
1
Instruction Set  
Code  
Instruction  
SAMPLE-Z  
IDCODE  
Notes  
000  
001  
010  
011  
100  
101  
110  
111  
1
1
SAMPLE-Z  
BYPASS  
SAMPLE  
PRIVATE  
BYPASS  
BYPASS  
1
3
4
3, 5  
3
3
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.  
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.  
3. BYPASS register is initialized to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded  
TDI when exiting the Shift DR state.  
4. SAMPLE instruction does not place DQs in High-Z.  
5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.  
List of IEEE 1149.1 standard violations:  
• 7.2.1.b, e  
• 7.7.1.a-f  
• 10.1.1.b, e  
• 10.7.1.a-d  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
03H9040  
SA14-4659-04  
Revised 7/96  
Page 15 of 21  
 
 
 
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