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IBM0364804PT3B-360 参数 Datasheet PDF下载

IBM0364804PT3B-360图片预览
型号: IBM0364804PT3B-360
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 72 页 / 1201 K
品牌: IBM [ IBM ]
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Discontinued (8/99 - last order; 12/99 - last ship)  
IBM0364804 IBM0364164  
IBM0364404 IBM03644B4  
64Mb Synchronous DRAM - Die Revision B  
Current State Truth Table (Part 2 of 4)(See note 1)  
Command  
Current State  
Action  
Notes  
CS RAS CAS WE A12,A13  
A11 - A0  
Description  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code  
Mode Register Set  
ILLEGAL  
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
Terminate Burst; Start the Precharge  
ILLEGAL  
L
H
L
Row Address Bank Activate  
4
Write  
H
H
H
H
X
L
Column  
Write  
Terminate Burst; Start a new Write cycle 8, 9  
L
H
L
Column  
Read  
Terminate Burst; Start the Read cycle  
Terminate the Burst  
Continue the Burst  
8, 9  
H
H
X
L
X
X
X
Burst Termination  
No Operation  
Device Deselect  
Mode Register Set  
H
X
L
X
X
Continue the Burst  
OP Code  
ILLEGAL  
L
L
H
L
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
4
4
4
4
L
H
L
Row Address Bank Activate  
ILLEGAL  
Read with  
Auto Pre-  
charge  
H
H
H
H
X
L
Column  
Write  
ILLEGAL  
L
H
L
Column  
Read  
ILLEGAL  
H
H
X
L
X
X
X
Burst Termination  
No Operation  
Device Deselect  
Mode Register Set  
ILLEGAL  
H
X
L
X
Continue the Burst  
Continue the Burst  
ILLEGAL  
X
OP Code  
L
L
H
L
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
4
4
4
4
L
H
L
Row Address Bank Activate  
ILLEGAL  
Write with  
Auto Pre-  
charge  
H
H
H
H
X
Column  
Write  
ILLEGAL  
L
H
L
Column  
Read  
ILLEGAL  
H
H
X
X
X
X
Burst Termination  
No Operation  
Device Deselect  
ILLEGAL  
H
X
X
Continue the Burst  
Continue the Burst  
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-  
mand is being applied to.  
2. All Banks must be idle; otherwise, it is an illegal action.  
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode  
is entered.  
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being  
referenced by the Current State then the action may be legal depending on the state of that bank.  
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.  
6. The minimum and maximum Active time (tRAS) must be satisfied.  
7. The RAS to CAS Delay (tRCD) must occur before the command is given.  
8. Column address A10 is used to determine if the Auto Precharge function is activated.  
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.  
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
19L3264.E35855A  
1/28/99  
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