Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Command Truth Table (See note 1)
CKE
A12,
A13
A11, A9-
A0
Function
Device State
CS RAS CAS WE
DQM
A10
Notes
Previous Current
Cycle
Cycle
Mode Register Set
Auto (CBR) Refresh
Entry Self Refresh
Idle
Idle
Idle
H
H
H
X
H
L
L
L
L
H
L
L
L
L
L
L
H
H
X
H
X
X
X
OP Code
X
X
X
X
X
X
L
L
X
H
X
H
Idle (Self-
Refresh)
Exit Self Refresh
L
H
X
X
X
X
See Current
State Table
Single Bank Precharge
Precharge all Banks
H
H
X
X
L
L
L
L
H
H
L
L
X
X
BS
X
L
X
X
2
See Current
State Table
H
Bank Activate
Write
Idle
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
L
H
L
H
L
X
X
X
X
X
X
X
X
BS
BS
BS
BS
BS
X
Row Address
2
2
Active
H
H
H
H
H
H
X
L
H
L
Column
Column
Column
Column
X
Write with Auto-Precharge Active
Read Active
Read with Auto-Precharge Active
L
L
2
L
H
H
L
2
L
H
X
X
X
2
Burst Termination
No Operation
Active
Any
H
H
X
3, 8
H
X
X
X
Device Deselect
Any
X
X
Clock Suspend Mode
Entry
Active
H
L
X
X
X
X
X
X
X
X
4
5
Clock Suspend Mode Exit Active
Data Write/Output Enable Active
Data Mask/Output Disable Active
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
H
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.Oper-
ation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other
deck. Refer to the Current State Truth Table.
2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 0,1 selects bank 1; BS0, BS1 = 1,0 selects bank 2; BS0, BS1
= 1,1 selects bank 3.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock tim-
ing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode.(If this command is issued during a burst operation, the
device state will be Clock Suspend Mode.)The Power Down Mode does not perform any refresh operations, therefore the device
can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect command is required on the next clock edge following CKE going high.
8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 32 of 72
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