Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Mode Register Operation (Address Input For Mode Set)
A13 A12 A11 A10 A9
Address Bus (Ax)
Mode Register(Mx)
A8
A7
A6
A5
A4
A3
A2
A1
A0
Operation Mode
CAS Latency
BT
Burst Length
Burst Type
M3
0
Type
Sequential
Interleave
1
Operation Mode
Burst Length
M13 M12 M11 M10 M9 M8 M7
Mode
Length
M2 M1 M0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Normal
Sequential Interleave
Multiple Burst with
Single Write
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
CAS Latency
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
M6 M5 M4
Latency
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 9 of 72
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