Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Automatic Refresh Command (CAS Before RAS Refresh)
When CS, RAS and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters
the Automatic Refresh mode (CBR). Both banks of the SDRAM must be precharged and idle for a minimum
of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. For a stacked device,
only one deck at a time can be refreshed using Automatic Refresh Mode. An address counter, internal to the
device, supplies the bank address during the refresh cycle. No control of the external address pins is required
once this cycle has started.
When the refresh cycle has completed, both banks of the SDRAM will be in the precharged (idle) state. A
delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto
Refresh Command must be greater than or equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command
is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the
Command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM
has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is
internally disabled during Self Refresh Operation to save power. The user may halt the external clock while
the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self
Refresh operation. Once the clock is cycling, the exit command will be registered asynchronously by bringing
CKE high. After CKE is brought high, an internal timer is started to insure CKE is held high for approximately
10ns before registering the Self Refresh exit command. The purpose of this circuit is to filter out noise glitches
on the CKE input which may cause the SDRAM to erroneously exit Self Refresh operation. Once the Self
Refresh command is registered, a delay equal to the RAS cycle time (tRC) must be satisfied before any new
command can be issued to the device. CKE must remain high for the entire Self Refresh exit period (tSREX
and commands must be gated off with CS held high. Alternatively, NOP commands may be registered on
each positive clock edge during the Self Refresh exit interval. (See Self Refresh Exit figures.) When using
Self Refresh, both decks of a stacked device may be refreshed at the same time.
)
Self Refresh Exit (Commands Gated Off with CS High)
T
T
T
T
T
T
T
T
T
m
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+8
CLK
CKE
CS
tRC
COMMAND
Any
Command
Self Refresh
Exit
: “H” or “L”
Begin Self Refresh Exit
Self Refresh
Exit Command
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 33 of 120
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