Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tRP
tDPL
tDAL
*
CAS latency = 3
CK3,DQs
t
DIN Ax
DIN Ax
DIN Ax
2
0
1
(-80, -10)
Bank can be reactivated at completion of tDAL
.
*
When CAS latency is set to equal 3 and tDPL = 2 clocks, the last write data that will be properly stored in the
device is that write data that is presented to the device two clocks prior to the Precharge command. The write
data presented during the clock cycle prior to the Precharge command may be stored incorrectly. To prevent
the writing of invalid data to the device, DQM must be asserted high one clock cycle prior to the Precharge
command to mask the invalid write data.
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 3
tCK3,
DQs
DIN Ax
DIN Ax
1
0
-360
(
)
DQM is needed to mask
the invalid data
Bank can be reactivated at completion of tDAL
.
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 32 of 120
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