Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Burst write operations will be terminated by the Precharge command. However, write data written to the
device prior to the Precharge command may be stored incorrectly and is a function of CAS latency and tDPL
.
When CAS latency is set to equal 1 or 2 or when set to 3 with tDPL = 1 clock, the last write data that will be
properly stored in the device is that write data that is presented to the device on the clock cycle prior to the
Precharge command. The write data presented during the Precharge command will not be written.
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 1)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 1
t
CK1, DQs
DIN Ax
DIN Ax
DIN Ax
2
0
1
Bank can be reactivated at completion of t
DAL
*
Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax
COMMAND
0
tDPL
tRP
tDAL
*
CAS latency = 2
t
CK2, DQs
DIN Ax
DIN Ax
DIN Ax
2
0
1
Bank can be reactivated at completion of tDAL
.
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 31 of 120
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