Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Command Truth Table (Notes: 1)
CKE
Function
CS
RAS
CAS
WE
DQM A11
A10
A9 - A0
Notes
Previous Current
Cycle
H
H
H
L
Cycle
Mode Register Set
Auto (CBR) Refresh
Entry Self Refresh
Exit Self Refresh
X
L
L
L
H
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
L
L
L
L
L
H
H
X
L
X
OP Code
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
L
H
X
X
L
X
H
H
H
L
X
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
L
BS
X
2
X
L
L
H
X
L
H
L
BS
BS
BS
BS
BS
X
Row Address
2
2
2
2
2
3
Write
X
H
H
H
H
H
H
X
X
X
X
X
X
L
H
L
Column
Write with Auto-Precharge
Read
X
L
L
Column
X
L
H
H
L
Column
Read with Auto-Precharge
Burst Termination
X
L
H
X
X
X
X
X
X
X
X
Column
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation
X
H
X
X
X
X
X
X
X
Device Deselect
X
X
Clock Suspend/Standby Mode
Data Write/Output Enable
Data Mask/Output Disable
Power Down Mode Entry
Power Down Mode Exit
X
X
4
5
H
H
X
X
X
X
H
X
X
X
5
L
X
6, 7
6, 7
X
H
X
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. For
stacked devices: only one deck can be operated at once, except during Self Refresh.
2. Bank Select (BS), if BS = 0 then bank A is selected, if BS = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock tim-
ing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Precharge Power Down Mode. If banks are active, Active Power Down Mode is
entered. The Power Down Mode does not perform any refresh operations, therefore the device can’t remain in this mode longer
than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. If CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 37 of 120
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