Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank separately or both banks simultaneously. Two
address bits A10 and A11 (BS) are used to define which bank(s) is to be precharged when the command is
issued.
Bank Selection for Precharge by Address Bits
A10
LOW
LOW
HIGH
BS(A11)
LOW
Precharged Bank(s)
Bank A only
HIGH
Bank B only
DON’T CARE
Both Banks A and B
For read cycles, the Precharge Command may be applied consistent with the CAS Latency set in the Mode
Register. The data DQs go to a high impedance state after a delay which is equal to the latency, similar to a
Burst Stop Command. Refer to the following figures.
For write cycles, however, a delay must be satisfied from the start of the last burst write cycle until the Pre-
charge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (tRP).
Burst Read followed by Precharge Command (Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
0
tRP
*
CAS latency = 2
DOUT Ax
DOUT Ax
DOUT Ax
DOUT Ax
3
0
1
2
t
CK2, DQs
Bank can be reactivated at completion of t
.
RP
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 25 of 120
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