Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Block Diagram (2Mbit x 4 I/O x 2 Bank)
Row Decoder
2048 x 1024
2048
Memory Bank A
CKE
CKE Buffer
Self
Refresh Clock
1024
Row
Address
Counter
Bank A
Row/Column
Select
Sense Amplifiers
Column Decoder and DQ Gate
4
11
Predecode A
Sequential
Control
Bank A
8
Data Input/Output Buffers
CLK
CLK Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Address Buffers (12)
12
3
Data Latches
8
12
11
Mode Register
8
DQ0
DQ1
DQ2
DQ3
CS
CS Buffer
3
Sequential
Control
Bank B
Data Latches
11
Predecode B
8
Command Decoder
RAS
RAS Buffer
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Sense Amplifiers
WE
WE Buffer
Row Decoder
2048
2048
Memory Bank B
2048 x 1024
DQM
DQM Buffer
1024
CAS
CAS Buffer
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 6 of 120
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